Group III nitride compound semiconductor and method for manufacturing the same

ABSTRACT

A sapphire substrate  1  is etched so that each trench has a width of 10 μm and a depth of 10 μm were formed at 10 μm of intervals in a stripe pattern. Next, an AlN buffer layer  2  having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate  1 . Then a GaN layer  3  is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer  21 , which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer  3  formed above the top surfaces of the mesas having a depth of 10 μm exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.

TECHNICAL FIELD

[0001] The present invention relates to a method for fabricating GroupIII nitride compound semiconductors. More particularly, the presentinvention relates to a method for fabricating Group III nitride compoundsemiconductors employing epitaxial lateral overgrowth (ELO), Group IIInitride compound semiconductor devices, and to Group III nitridecompound semiconductor substrates. The Group III nitride compoundsemiconductors are generally represented by Al_(x)Ga_(y)In_(1−x−y)N(wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1), and examples thereof include binarysemiconductors such as AlN, GaN, and InN; ternary semiconductors such asAl_(x)Ga_(1−x)N, Al_(x)In_(1−x)N, and Ga_(x)In_(1−x)N (wherein 0<x<1);and quaternary semiconductors such as Al_(x)Ga_(y)In_(1−x−y)N (wherein0<x<1, 0<y<1, and 0<x+y<1).

[0002] In the present specification, unless otherwise specified, “GroupIII nitride compound semiconductors” encompass Group III nitridecompound semiconductors which are doped with an impurity so as to assumep-type or n-type conductivity.

BACKGROUND ART

[0003] Group III nitride compound semiconductor are direct-transitionsemiconductors exhibiting a wide range of emission spectra from UV tored light when used in a device such as a light-emitting device, andhave been used in light-emitting devices such as light-emitting diodes(LEDs) and laser diodes (LDs). In addition, due to their broad bandgaps, devices employing the aforementioned semiconductors are expectedto exhibit reliable operational characteristics at high temperature ascompared with those employing semiconductors of other types, and thusapplication thereof to transistors such as FETs has been energeticallystudied. Moreover, since Group III nitride compound semiconductorscontain no arsenic (As) as a predominant element, application of GroupIII nitride compound semiconductors to various semiconducting deviceshas been longed for from the environmental aspect. Generally, theseGroup III nitride compound semiconductors are formed on a sapphiresubstrate.

DISCLOSURE OF THE INVENTION

[0004] However, when a Group III nitride compound semiconductor isformed on a sapphire substrate, misfit-induced dislocations occur due todifference between the lattice constant of sapphire and that of thesemiconductor, resulting in poor device characteristics. Misfit-induceddislocations are threading dislocations which penetrate semiconductorlayers in a longitudinal direction (i.e., in a direction vertical to thesurface of the substrate), and Group III nitride compound semiconductorsare accompanied by the problem that dislocations in amounts ofapproximately 10⁹ cm⁻² propagate therethrough. The aforementioneddislocations propagate through layers formed from Group III nitridecompound semiconductors of different compositions, until they reach theuppermost layer. When such a semiconductor is incorporated in, forexample, a light-emitting device, the device poses problems ofunsatisfactory device characteristics in terms of threshold current ofan LD, service life of an LED or LD, etc. On the other hand, when aGroup III nitride compound semiconductor is incorporated in any of othertypes of semiconductor devices, because electrons are scattered due todefects in the Group III nitride compound semiconductor, thesemiconductor device comes to have low mobility. These problems are notsolved even when another type of substrate is employed.

[0005] The aforementioned dislocations will next be described withreference to a sketch of FIG. 18. FIG. 18 shows a substrate 91, a bufferlayer 92 formed thereon, and a Group III nitride compound semiconductorlayer 93 further formed thereon. Conventionally, the substrate 91 isformed of sapphire or a similar substance and the buffer layer 92 isformed of aluminum nitride (AlN) or a similar substance. The bufferlayer 92 formed of aluminum nitride (AlN) is provided so as to relaxmisfit between the sapphire substrate 91 and the Group III nitridecompound semiconductor layer 93. However, generation of dislocations isnot reduced to zero. Threading dislocations 901 propagate upward (in avertical direction with respect to the substrate surface) fromdislocation initiating points 900, penetrating the buffer layer 92 andthe Group III nitride compound semiconductor layer 93. When asemiconductor device is fabricated by stacking various types of GroupIII nitride compound semiconductors of interest on the Group III nitridecompound semiconductor layer 93, threading dislocations furtherpropagate upward, through the semiconductor device, from dislocationarrival points 902 on the surface of the Group III nitride compoundsemiconductor layer 93. Thus, according to conventional techniques,problematic propagation of dislocations cannot be prevented duringformation of Group III nitride compound semiconductor layers.

[0006] The present invention has been accomplished in an attempt tosolve the aforementioned problems, and an object of the presentinvention is to fabricate a Group III nitride compound semiconductorwith suppressed generation of threading dislocations.

[0007] In order to attain the aforementioned object, the invention drawnto a first feature provides a method for fabricating a Group III nitridecompound semiconductor on a substrate, which comprises removing at leasta portion of the surface of the substrate so as to provide a trench/postor trench/mesa on the surface of the substrate, and epitaxially growing,vertically and laterally, a desired Group III nitride compoundsemiconductor on a not removed surface of said substrate, so as to coverthe upper portion above said trench of the substrate, with a top surfaceof the surface of the substrate which was not removed serving as a seed,the not removed surface of the substrate being formed by removing aportion of the substrate so as to form an island-like structure such asa dot-like, stripe-shaped, or grid-like structure.

[0008] The invention drawn to a second feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises removing at least a portion of thesurface of the substrate, so as to provide a trench/post on the surfaceof the substrate, forming a buffer layer on the substrate, andepitaxially growing, vertically and laterally, a desired Group IIInitride compound semiconductor, so as. to cover the upper portion of thetrench of the trench/post of the substrate, with the buffer layer formedon the remaining surface of the substrate serving as a seed or nucleusfor crystal growth, the buffer layer being formed in an island-likestructure such as a dot-like, stripe-shaped, or grid-like structure.

[0009] The invention drawn to a third feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises removing at least a portion of thesurface of the substrate, so as to provide a trench/post on the surfaceof the substrate, forming a buffer layer on the substrate, epitaxiallygrowing, vertically, a Group III nitride compound semiconductor on thebuffer layer so as to form a monocrystalline layer, and epitaxiallygrowing, vertically and laterally, a desired Group III nitride compoundsemiconductor, so as to cover the upper portion of the trench of thetrench/post of the substrate, with the monocrystalline layer of GroupIII nitride compound semiconductor formed on the buffer layer on theremaining surface of the substrate serving as a seed for crystal growth,the monocrystalline layer being formed in an island-like structure suchas a dot-like, stripe-shaped, or grid-like structure.

[0010] The invention drawn to a fourth feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises forming a buffer layer on the substrate,removing at least a portion of the buffer layer and the surface of thesubstrate so as to provide a trench/post having a post or a mesa onwhich the buffer layer is formed on the surface of the substrate and atrench on which the buffer layer is not formed, and epitaxially growing,vertically and laterally, a desired Group III nitride compoundsemiconductor, so as to cover the upper portion of the trench of thetrench/post of the substrate, with a buffer layer formed on theremaining surface of the substrate serving as a seed for crystal growth,the buffer layer being formed in an island-like structure such as adot-like, stripe-shaped, or grid-like structure.

[0011] The invention drawn to a fifth feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises forming a buffer layer on the substrate,epitaxially growing, vertically, a Group III nitride compoundsemiconductor on the buffer layer so as to form a monocrystalline layer,removing at least a portion of the monocrystalline layer of Group IIInitride compound semiconductor, the buffer layer, and the surface of thesubstrate so as to provide a trench/post having a post on which themonocrystalline layer of Group III nitride compound semiconductor andthe buffer layer is formed on the surface of the substrate and a trenchon which the monocrystalline layer of Group III nitride compoundsemiconductor and the buffer layer are not formed, and epitaxiallygrowing, vertically and laterally, a desired Group III nitride compoundsemiconductor, so as to cover the upper portion of the trench of thetrench/post of the substrate, with the monocrystalline layer of GroupIII nitride compound semiconductor formed on the buffer layer on theremaining surface of the substrate serving as a seed for crystal growth,the monocrystalline layer being formed in an island-like structure suchas a dot-like, stripe-shaped, or grid-like structure.

[0012] The invention drawn to a sixth feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on the substrate, whichcomprises a surface treatment process of decreasing smoothness of atleast a portion of the surface of the substrate and forming a portion onwhich a Group III nitride compound semiconductor layer is notsufficiently to be formed on the surface of the substrate, a process ofgrowing the Group III nitride compound semiconductor on said treatedsubstrate and forming a portion where a monocrystalline layer of GroupIII nitride compound semiconductor is sufficiently formed and a portionwhere a monocrystalline layer of Group III nitride compoundsemiconductor is not sufficiently formed, and a process of epitaxiallygrowing, vertically and laterally, Group III nitride compoundsemiconductor, so as to cover the portion where the monocrystallinelayer of Group III nitride compound semiconductor is not sufficientlyformed, with the monocrystalline layer of Group III nitride compoundsemiconductor formed on the portion of the substrate whose surfacesmoothness is not decreased serving as a seed for crystal growth, themonocrystalline layer being formed in an island-like structure such as adot-like, stripe-shaped, or grid-like structure.

[0013] The invention drawn to a seventh feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises a surface treatment process of decreasingsmoothness of at least a portion of the surface of the substrate andforming a portion where a buffer layer is sufficiently to be formed onthe surface of the substrate, a process of growing the buffer layer onthe treated substrate and forming a portion on which a buffer layer issufficiently formed and a portion where a buffer layer is notsufficiently formed, and a process of epitaxially growing, verticallyand laterally, a desired Group III nitride compound semiconductor, so asto cover the portion where the buffer layer is not sufficiently formed,with the buffer layer formed on the portion of the substrate whosesurface smoothness is not decreased serving as a seed for crystalgrowth, the buffer layer being formed in an island-like structure suchas a dot-like, stripe-shaped, or grid-like structure.

[0014] The invention drawn to an eighth feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises a surface treatment process of decreasingsmoothness of at least a portion of the surface of the substrate andforming a portion on which a buffer layer is sufficiently to be formedon the surface of the substrate, a process of growing the buffer layeron the treated substrate and forming a portion where a buffer layer issufficiently formed and a portion where a buffer layer is notsufficiently formed, a process of forming a monocrystalline layer ofGroup III nitride compound semiconductor on the portion where the bufferlayer is sufficiently formed, and a process of epitaxially growing,vertically and laterally, a desired Group III nitride compoundsemiconductor, so as to cover the portion where the buffer layer is notsufficiently formed, with the monocrystalline layer of the Group IIInitride compound semiconductor formed on the buffer layer formed on theportion of the substrate whose surface smoothness is not decreasedserving as a seed for crystal growth, the monocrystalline layer of theGroup III nitride compound semiconductor being formed in an island-likestructure such as a dot-like, stripe-shaped, or grid-like structure.

[0015] The invention drawn to a ninth feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises a process of forming a buffer layer on asubstrate, a surface treatment process of decreasing smoothness of atleast a portion of the surface of the buffer layer and forming a portionon which a monocrystalline layer of Group III nitride compoundsemiconductor is not sufficiently to be formed, a process of epitaxiallygrowing, vertically and laterally, a desired Group III nitride compoundsemiconductor, so as to cover the portion where smoothness of the bufferlayer is decreased, with the portion of the buffer layer whose surfacesmoothness is not decreased serving as a seed for crystal growth, theportion of the buffer layer being formed in island-like structure suchas a dot-like, stripe-shaped, or grid-like structure.

[0016] In the invention drawn to a tenth feature provides a method forfabricating a Group III nitride compound semiconductor in which a GroupIII nitride compound semiconductor is grown on a buffer layer formed onthe substrate, which comprises a process of forming a buffer layer on asubstrate, a process of forming a first Group III nitride compoundsemiconductor on the buffer layer, a surface treatment process ofdecreasing smoothness of at least a portion of the first Group IIInitride compound semiconductor and forming a portion on which amonocrystalline layer of a second Group III nitride compoundsemiconductor is not sufficiently to be formed, and a process ofepitaxially growing, vertically and laterally, the second Group IIInitride compound semiconductor, so as to cover the portion wheresmoothness of the first Group III nitride compound semiconductor isdecreased, with the portion of the first Group III nitride compoundsemiconductor whose surface smoothness is not decreased serving as aseed for crystal growth, the portion of the first Group III nitridecompound semiconductor being formed in an island-like structure such asa dot-like, stripe-shaped, or grid-like structure.

[0017] The invention drawn to an eleventh feature provides a Group IIInitride compound semiconductor device, which is formed as an upper layerprovided on a lateral-epitaxially grown portion of a Group III nitridecompound semiconductor layer produced through a method for fabricating aGroup III nitride compound semiconductor in connection with any one ofthe first to tenth features.

[0018] The invention drawn to a twelfth feature provides a Group IIInitride compound semiconductor light-emitting device, which is producedby stacking, as an upper layer, a different Group III nitride compoundsemiconductor layer on a lateral-epitaxially grown portion of a GroupIII nitride compound semiconductor layer produced through a method forfabricating a Group III nitride compound semiconductor as recited inconnection with any one of the first to tenth features.

[0019] The invention drawn to a thirteenth feature provides a method forfabricating a Group III nitride compound semiconductor substrateincluding a method for fabricating a Group III nitride compoundsemiconductor as recited in connection with any one of the first totenth features and removing substantially entire portions except for anupper layer formed on a portion provided through lateral epitaxialgrowth, to thereby obtain a Group III nitride compound semiconductorsubstrate.

[0020] The outline of an example of the method for fabricating a GroupIII nitride compound semiconductor of the present invention will next bedescribed with reference to FIGS. 1-11.

[0021] [Invention According to First to Third Features]

[0022] As shown in FIG. 1(a), the substrate 1 is removed to thereby forman island-like structure such as a stripe-shaped, or grid-likestructure, so as to provide a trench/post. Next, the buffer layer 2 isformed. The example when a buffer layer 2 comprises a portion 21 whichis formed mainly on the upper surface of the post on the substrate 1 anda portion 22 which is formed on the bottom surface of the trench willnext be described with reference to FIG. 1(b).

[0023] As shown in FIG. 1(b), the Group III nitride compoundsemiconductor 3 is epitaxially grown, vertically and laterally, with thebuffer layer 2 comprising a portion 21 formed on the upper surface ofthe post and a portion 22 formed on the bottom surface of the trench ofthe substrate 1 serving as a seed for crystal growth, the substrate 1having the trench of an island-like structure such as a stripe-shaped,or grid-like structure. Then, as shown in FIG. 1(c), the Group IIInitride compound semiconductor 31, with the buffer layer 21 formed onthe upper surface of the post serving as a seed or nucleus for crystalgrowth, can cover the upper portion of the trench before the Group IIInitride compound semiconductor 32, which grows from the buffer layer 22formed on the. bottom surface of the trench, buries the trench. Further,by epitaxially growing, vertically or laterally, the Group III nitridecompound semiconductor 3, the upper portion of the trench of thesubstrate is covered by the epitaxial growth as shown in FIG. 1(d), anda concentration of threading dislocations propagating in verticaldirection extremely decreases.

[0024] When the rate that the Group III nitride compound semiconductor31, which epitaxially grows in lateral direction from the buffer layer21 formed on the upper surface of the post or mesa, coalescences to thelateral epitaxial growth layer starting from the upper surface of thepost facing to each other is faster than the rate that the Group IIInitride compound semiconductor 32, which epitaxially grows in verticaldirection from the buffer layer 22 formed on the bottom surface of thetrench, grows to the upper layer of the post, threading dislocationspropagated from the buffer layer 22 formed on the bottom layer of thetrench is remarkably suppressed in the upper portion of the thus-buriedGroup III nitride compound semiconductor 31, to thereby provide acrystal region of remarkably high quality. In this case, as shown inFIG. 1(d), the growth front of the Group III nitride compoundsemiconductor 32 which is grown from the buffer layer 22 formed on thebottom portion of the trench serving as a seed for crystal growth is notexposed at the surface but remains as cavities. And over the cavities,growth fronts of the Group III nitride compound semiconductor 31 grownfrom the buffer layer, formed on the upper layer of the post of bothsides and serving as seeds for crystal growth, coalesce. The propagationof threading dislocations from the buffer layer 22 can be prevented atthe cavities.

[0025] In FIG. 1(b), the buffer layer is hardly formed on the sidewallsof the trench of the substrate 1. Next, the case when the buffer layeris formed on the sidewalls of the trench of the substrate 1 as shown inFIGS. 2(a)-2(d) is explained hereinafter. As illustrated in FIG. 1(a),trenches/posts are formed by etching the substrate 1 (FIG. 2(a)). Then,as shown in FIG. 2(b), a Group III nitride compound semiconductor 3epitaxially grows, vertically and laterally, with the buffer layer 2,which is formed on the upper surface of the post, the lower surface ofthe trench, and sidewalls of the trench of the substrate 1 formed tohave an island-like structure such as a dot-like, stripe-shaped, orgrid-like structure, serving as seeds for crystal growth. As shown inFIG. 2(c), the Group III nitride compound semiconductor 3, whichepitaxially grows from the buffer layer 2 at the bottom surface andsidewalls of the trenches in vertical direction, buries the trenches,and the Group III nitride compound semiconductor 3 which grows from theupper surface of the posts of the buffer layer 2 in lateral directiongrows so as to cover the trenches. Here “growing in vertical direction”from the sidewalls of the trenches means to grow in a direction normalto the sidewalls of the trench. Then, as illustrated in FIG. 1(d), theupper portion of the trench of. the substrate is occupied by the GroupIII nitride compound semiconductor 3, which grows vertically from thebuffer layer 2 formed on the sidewall of the trench and buries thetrench, and the Group III nitride compound semiconductor 3, which growslaterally from the buffer layer 2 formed on the upper surface of thepost. Threading dislocations of the Group III nitride compoundsemiconductor 3, which grows vertically on the buffer layer 2 formed onthe sidewalls of the trench, in vertical direction is normal directionof the sidewall of the trench, and a concentration of threadingdislocations propagating from the substrate surface (the upper surfaceof the post or the bottom surface of the trench) in vertical directionextremely decreases.

[0026] When the Group III nitride compound semiconductor 3 whichepitaxially grows in lateral direction from the buffer layer formed onthe upper surface of the post coalescences more rapidly compared withthat the Group III nitride compound semiconductor 3 which epitaxiallygrows in vertical direction from the buffer layer 2 formed on the bottomsurface of the trench grows to the upper layer of the post, thepropagation of the threading dislocations from the buffer layer 2 in theupper portion of the thus-buried Group III nitride compoundsemiconductor 3 is remarkably suppressed, to thereby provide a crystalregion of remarkably high quality. In this case, as shown in FIG. 2(d),growth fronts of the Group III nitride compound semiconductor 3 grownfrom the buffer layer 2 on the bottom surface of the trench, serving asseeds for crystal growth, are not come out to the surface but remain ascavities. And over the cavities, growth fronts of the Group III nitridecompound semiconductor 3 grown from the buffer layer 2 on the post,serving as seeds for crystal growth, coalesce and the threadingdislocations propagated from the buffer layer 2 on the bottom of thetrench are prevented by this cavities.

[0027] The aforementioned rapid lateral epitaxial growth can be readilyattained when the Group III nitride compound semiconductor layer 31assumes a {11-20} plane as a growth front of the sidewall of the trench.During lateral epitaxial growth, at least an upper portion of the growthfront may preferably remain a {11-20} plane. Of course the lateralepitaxial growth front cannot be limited to the {11-20} plane of theGroup III nitride compound semiconductor.

[0028] The procedure described above can be applied to a Group IIInitride compound semiconductor which epitaxially grows not on a bufferlayer but directly on a substrate. FIGS. 3(a)-3(c) illustrate theprocedure of removing a part of the substrate 1 to form trenches (FIG.3(a)), growing the Group III nitride compound semiconductor 3 verticallyand laterally (FIG. 3(b)), and covering the trench by lateral growth ofa portion formed on the upper surface of the post with the Group IIInitride compound semiconductor 3 serving as a seeds for crystal growth(FIG. 3(c)). And as shown in FIGS. 4(a)-4(d), a monocrystalline layer 3of Group III nitride compound semiconductor (a monocrystalline layer 31which is the upper layer of the post and a monocrystalline layer 32which is the bottom layer of the trench) can be formed on the bufferlayer 2 (a buffer layer 21 which is the upper layer of the post and abuffer layer 22 which is the bottom layer of the trench) (FIG. 4(b)),thereby covering the trench by lateral growth with the monocrystallinelayer 31 of the upper layer of the post serving as a seed for crystalgrowth (FIGS. 4(c) and 4(d)).

[0029] [Invention According to Fourth and Fifth Features]

[0030] As shown in FIG. 5(a), the buffer layer 2 is formed on thesubstrate 1. Then as shown in FIG. 5(b), portions of the buffer layer 2and the substrate 1 are removed, so as to provide trenches/posts. Asshown in FIG. 5(c), a Group III nitride compound layer 31 is epitaxiallygrown, vertically and laterally, with mainly the buffer layer 2 servingas a seed for crystal growth. FIG. 5(c) illustrates the Group IIInitride compound semiconductor 32 growing epitaxially from the bottomsurfaces and sidewalls of the trenches/posts. When the rate that theGroup III nitride compound semiconductor 31, which epitaxially grows inlateral direction from the buffer layer 2 formed on the upper surface ofthe post, coalescences to the lateral epitaxial growth front startingfrom the upper surface of the post facing to each other is faster thanthe rate that the Group III nitride compound semiconductor 32, whichepitaxially grows in vertical direction from the buffer layer 2 formedon the bottom surface and the sidewall of the trench, grows to the upperlayer of the post, threading dislocations propagated from the bottomlayer of the trench is remarkably suppressed in the upper portion of thethus-buried Group III nitride compound semiconductor 31, to therebyprovide a crystal region of remarkably high quality. In this case, asshown in FIG. 5(d), the growth layer of the Group III nitride compoundsemiconductor 32 which is grown from the buffer layer 2 formed on thebottom portion of the trench serving as a seed for crystal growth is notexposed at the surface but remains as cavities. And over the cavities,growth fronts of the Group III nitride compound semiconductor 31 grownfrom the buffer layer 2, formed on the upper layer of the post of bothsides and serving as seeds for crystal growth, coalesce. The propagationof threading dislocations from the buffer layer 2 can be prevented atthe cavities.

[0031] The aforementioned rapid lateral epitaxial growth can be readilyattained when growth front of the Group III nitride compoundsemiconductor layer 31 parallel to the sidewall of the trench assumes a{11-20} plane. During lateral epitaxial growth, at least an upperportion of the growth front may preferably remain a {11-20} plane. Ofcourse the lateral epitaxial growth front cannot be limited to the{11-20} plane of the Group III nitride compound semiconductor.

[0032] As shown in FIGS. 6(a)-6(d), a buffer layer 2 and amonocrystalline layer 31 of the Group III nitride compound semiconductorare formed (FIG. 6(a)), a trench is formed (FIG. 6(b)), to therebycovering the trench by lateral growth with the monocrystalline layer 31of the upper layer of the post serving as a seed for crystal growth(FIGS. 6(c) and 6(d)).

[0033] [Invention According to Sixth to Eighth Features]

[0034] As shown in FIG. 7(a), rugged portions A which are roughened bye.g., etching or scribing, are formed on the surface of the substrate 1,so that the other portions of the substrate surface, which are notrugged, becomes an island-like structure such as a stripe-shaped orgrid-like structure. Then a buffer layer 2 is formed on the substrate 1.Compared with a buffer layer 21 formed on the portion without ruggednessof the surface, the surface layer of the buffer layer 22 formed on therugged portion A of the substrate surface cannot be a uniformmonocrystalline layer and, moreover, its growth velocity is rather slow(FIG. 7(b)). When a Group III nitride compound semiconductor 3 isepitaxially grown vertically and laterally thereon, a monocrystallinelayer is formed rapidly with the buffer layer 21, which is mainly formedon the portion of the substrate 1 without ruggedness of the surface,serving as a seed for crystal growth, and the buffer layer 22 formed onthe rugged portion A is also covered by growing in lateral direction(FIG. 7(c)). By further growing the Group III nitride compoundsemiconductor 3 epitaxially in vertical and lateral directions, thebuffer layer 22 formed on the rugged portion A is completely covered bythe Group III nitride compound, semiconductor 3 epitaxially grown inlateral direction with the buffer layer 21, which is mainly formed onthe portion without ruggedness of the surface, serving as a seed forcrystal growth. In this case, threading dislocations in verticaldirection, generated from the buffer layer 22 which is formed on therugged portion A, are not propagated to the Group III nitride compoundsubstrate 3 which is grown thereon epitaxially in lateral direction.

[0035] As shown in FIG. 8(a), rugged portions A which are roughened bye.g., etching and etching or scribing, are formed on the surface of thesubstrate 1, so that the other portions of the substrate surface, whichare not rugged, becomes an island-like structure such as a stripe-shapedor grid-like structure. Then a Group III nitride compound semiconductor3, which grows epitaxially on the substrate 1, is formed thereon.Compared with a Group III nitride compound semiconductor 31 formed onthe portion without ruggedness of the surface, the surface layer in aGroup III nitride compound semiconductor 32 formed on the rugged portionA of the substrate surface cannot be a uniform monocrystalline layer andits growth velocity rather is slow (FIG. 8(b)). By further growing theGroup III nitride compound semiconductor 3 epitaxially in vertical andlateral directions, the upper portion of the Group III nitride compoundsemiconductor 32 which is formed on the rugged portion A is completelycovered by the Group III nitride compound semiconductor 31 growingepitaxially in lateral. direction. In this case, threading dislocationsin vertical direction, generated from the Group III nitride compoundsemiconductor 32 which is formed on the rugged portion A, are notpropagated to the Group III nitride compound substrate 31 which is grownthereon epitaxially in lateral direction.

[0036] In FIGS. 7(a)-7(d), only a single Group III nitride compoundsemiconductor 3 epitaxially grows, vertically and laterally, on thesubstrate 1. Further, as shown in FIGS. 9(a)-9(d), the buffer layer 21is formed on the portion without ruggedness of the surface, the GroupIII nitride compound semiconductor 31 is grown in vertical direction onthe buffer layer 21, serving as a monocrystalline layer, and the GroupIII nitride compound semiconductor 32 can be grown in vertical andlateral directions thereon with the monocrystalline layer 31 of GroupIII nitride compound semiconductor serving as a seed for crystal growth.

[0037] [Invention According to Ninth and Tenth Features]

[0038] As shown in FIGS. 10(a)-10(d), after forming a buffer layer 2 ona substrate 1 (FIG. 10(a)) and deteriorating its surface by etching orscribing (FIG. 10(b)), a Group III nitride compound semiconductor 3 canbe grown thereon in vertical and lateral directions (FIGS. 10(c) and10(d)). As shown in FIGS. 11(a)-11(d), after forming a buffer layer 2and a Group III nitride compound semiconductor 31 on a substrate 1 (FIG.11(a)) and deteriorating its surface by etching or scribing (FIG.11(b)), a Group III nitride compound semiconductor layer 33 can be grownthereon in vertical and lateral directions (FIGS. 11(c) and 11(d)). AGroup III nitride compound semiconductor layer formed on the portionwithout ruggedness of the surface grows faster than that formed on therugged portion of the substrate as shown in both FIG. 10(c) and FIG.11(c). By growing the Group III nitride compound semiconductor layer inlateral direction with portions of it formed on the portion withoutruggedness of the surface as seeds for crystal growth, the layer growsso as to cover the portions with rugged surface.

[0039] Through the procedure as described above there can be providedthe Group III nitride compound semiconductor in which threadingdislocations in propagated in vertical direction.

[0040] By forming a device element as an upper layer on a portion of aGroup III nitride compound semiconductor layer that is formed throughlateral epitaxial growth through the above step, there can be provided asemiconductor device having a layer containing few defects and endowedwith high mobility (eleventh feature).

[0041] By stacking, as an upper layer, a light-emitting element on aportion of a Group III nitride compound semiconductor layer that isformed through the above step, there can be provided a light-emittingdevice endowed with improved service life and improved LD thresholdvalue (twelfth feature).

[0042] By selectively separating, from the other layers, an upper layerformed on a portion of the Group III nitride compound semiconductorlayer that is provided through lateral epitaxial growth through theabove step, there can be produced a high-crystallinity Group III nitridecompound semiconductor in which crystal defects such as dislocations areremarkably suppressed (thirteenth feature). In this connection, for thesake of convenience in manufacture, the expression “removingsubstantially entire portions” does not exclude the case in which aportion containing threading dislocations is present to some extent.

BRIEF DESCRIPTION OF THE DRAWINGS

[0043]FIG. 1 is a series of sectional views showing the steps offabricating a Group III nitride compound semiconductor according to afirst embodiment of the present invention;

[0044]FIG. 2 is a series of sectional views showing the steps offabricating another Group III nitride compound semiconductor of thepresent invention;

[0045]FIG. 3 is a series of sectional views showing the steps offabricating a Group III nitride compound semiconductor according to aseventh embodiment of the present invention;

[0046]FIG. 4 is a series of sectional views showing the steps offabricating another Group III nitride compound semiconductor of thepresent invention;

[0047]FIG. 5 is a series of sectional views showing the steps offabricating a Group III nitride compound semiconductor light-emittingdevice according to a second embodiment of the present invention;

[0048]FIG. 6 is a series of sectional views showing the steps offabricating another Group III nitride compound semiconductor of thepresent invention;

[0049]FIG. 7 is a series of sectional views showing the steps offabricating a Group III nitride compound semiconductor according to thethird embodiment of the present invention;

[0050]FIG. 8 is a series of sectional views showing the steps offabricating another Group III nitride compound semiconductor of thepresent invention;

[0051]FIG. 9 is a series of sectional views showing the steps offabricating another different Group III nitride compound semiconductorof the present invention;

[0052]FIG. 10 is a series of sectional views showing the steps offabricating another different Group III nitride compound semiconductorof the present invention;

[0053]FIG. 11 is a series of sectional views showing the steps offabricating another different Group III nitride compound semiconductorof the present invention;

[0054]FIG. 12 is a series of sectional views showing the steps offabricating a Group III nitride compound semiconductor according to afourth embodiment of the present invention;

[0055]FIG. 13 is a sectional view showing a Group III nitride compoundsemiconductor light-emitting device according to a fifth embodiment ofthe present invention;

[0056]FIG. 14 is a sectional view showing a Group III nitride compoundsemiconductor light-emitting device according to a sixth embodiment ofthe present invention;

[0057]FIG. 15 is a sectional view showing a Group III nitride compoundsemiconductor light-emitting device according to a seventh embodiment ofthe present invention;

[0058]FIG. 16 is a sectional view showing a Group III nitride compoundsemiconductor light-emitting device according to an eighth embodiment ofthe present invention;

[0059]FIG. 17 is a schematic view showing another example of etching ofa first Group III nitride compound semiconductor; and

[0060]FIG. 18 is a sectional view showing threading dislocationspropagating in a Group III nitride compound semiconductor.

BEST MODE FOR CARRYING OUT THE INVENTION

[0061] Embodiments of the present invention will next be described withreference to the drawings. The present invention has the above-describedfeatures and is not limited to the embodiments which will be describedspecifically.

[0062] Each of FIGS. 1-8 schematically shows a mode for carrying out amethod for fabricating a Group III nitride compound semiconductor of thepresent invention. FIG. 1 shows an example in which a buffer layer 2 isnot formed on a diced sidewall of a substrate 1. A trench is formed bydicing the substrate 1 (FIG. 1(a)), a buffer layer is formed (FIG.1(b)), and a Group III nitride compound semiconductor layer 3 isepitaxially grown in lateral direction (FIG. (c)). Width and depth ofdicing shown in FIG. 1(a) are determined so that the Group III nitridecompound semiconductor layer 31, which grows vertically and laterally,with the buffer layer 21 formed on the upper surface of the post or mesaserving as a seed or nucleus for crystal growth, covers the upperportion of the trench before the Group III nitride compoundsemiconductor layer 32, which grows vertically with the buffer layer 2formed at the bottom surface of the trench serving as a seed for crystalgrowth, buries the trench as described above. In FIG. 1(c), a lateralepitaxial growth front is assumed to be, for example, {11-20} planes.But in the present invention, it is not limited to an orientation of agrowth front surface. Accordingly, the form of dicing and lateralepitaxial growth conditions are determined such that lateral growth ofthe Group III nitride compound semiconductor layer 31, with the bufferlayer 21 formed on the upper surface of the post serving as a seed forcrystal growth, coalescences at the upper portion of the trench formedby dicing before the vertical growth from the bottom surface of thetrench buries the diced portion, whereby threading dislocations issuppressed in the regions of the Group III nitride compoundsemiconductor layer 31 formed on the upper portion of the trenchobtained by dicing (FIG. 1(d)).

[0063]FIG. 2 illustrates structures when a buffer layer 2 is also formedat each sidewall. of the trenches. Other effects to be yielded aresimilar to those described previously in relation to the case of FIG. 1.

[0064]FIG. 5 illustrates an embodiment in which dicing is carried outafter forming the buffer layer 2 on the substrate 1. Without the bufferlayer 2, the bottom surface and the sidewalls of the trenches formed onthe substrate 1 does not grows vertically or grows at an extremely lowvelocity. Lateral growth, with the buffer layer 2 which is formed on theupper surface of the post serving as a seed for crystal growth, coversthe trenches formed by dicing (FIGS. 5(c) and 5(d)). As described above,width and depth of dicing shown in FIG. 2(a) are determined such thatlateral growth of the Group III nitride compound semiconductor layer 31,with the buffer layer 21 formed on the upper surface of the post servingas a seed for crystal growth, covers the upper portion of the trenchesbefore the vertical growth of the Group III nitride compoundsemiconductor layer 32 from the bottom surface of the trench buries thediced portion. In FIG. 2(c), a lateral epitaxial growth front is assumedto be, for example, {11-20} planes. But in the present invention, it isnot limited to an orientation of a growth front surface.

[0065]FIG. 7 shows a mode for forming the buffer layer 2 afterroughening the surface of the substrate 1. Area of rugged portions A isdetermined such that a Group III nitride compound semiconductor layer 3,with a buffer layer 21 formed on the portions without ruggedness of thesurface of the substrate 1 serving as a seed for crystal growth,epitaxially grows in vertical and lateral directions and covers a bufferlayer 22, whose surface layer cannot be a uniform monocrystalline layerand which has a low growth velocity, formed on the rugged portions A.

[0066]FIG. 8 shows a mode for forming a Group III nitride compoundsemiconductor directly after roughening the surface of the substrate 1.Area of rugged portions A is determined such that a Group .III nitridecompound semiconductor layer 31 formed on the portions withoutruggedness of the surface of the substrate 1 epitaxially grows invertical and lateral directions and covers a Group III nitride compoundsemiconductor layer 32, whose surface layer cannot be uniformmonocrystalline layer and which has a low growth velocity, formed on therugged portions A.

[0067] As an above-described mode for carrying out the invention allowselections to be described below.

[0068] When a laminate including a substrate and a Group III nitridecompound semiconductor is to be formed, the substrate may be aninorganic crystalline substrate of sapphire, silicon (Si), siliconcarbide (SiC), spinel (MgAl₂O₄), ZnO, MgO, or the like, and a GroupIII-V compound semiconductor, such as a gallium phosphide or galliumarsenide semiconductor, or a Group III nitride compound semiconductor,such as a gallium nitride (GaN) semiconductor, may be used.

[0069] A preferred process for forming a Group III nitride compoundsemiconductor layer is metal-organic chemical vapor deposition (MOCVD)or metal-organic vapor phase epitaxy (MOVPE). However, molecular beamepitaxy (MBE), halide vapor phase epitaxy (halide VPE), liquid phaseepitaxy (LPE), or the like may be used. Also, individual layers may beformed by different growth processes.

[0070] When a Group III nitride compound semiconductor layer is to beformed on, for example, a sapphire substrate, in order to impart goodcrystallinity to the layer, a buffer layer is preferably formed for thepurpose of correcting lattice mismatch with the sapphire substrate. Whena substrate of another material is to be used, employment of a bufferlayer is also preferred. A buffer layer is preferably of a Group IIInitride compound semiconductor Al_(x)Ga_(y)In_(1−x−y)N formed at lowtemperature (0≦x≦1, 0≦y≦1, 0≦x+y≦1), more preferably of Al_(x)Ga_(1−x)N(0≦x≦1). This buffer layer may be a single layer or a multi-componentlayer comprising layers of different compositions. A buffer layer may beformed at a low temperature of 380-420° C. or by MOCVD at a temperatureof 1000-1180° C. Alternatively, an AlN buffer layer can be formed by areactive sputtering process using a DC magnetron sputtering apparatusand, as materials, high-purity aluminum and nitrogen gas. Similarly, abuffer layer represented by the formula Al_(x)Ga_(y)In_(1−x−y)N (0≦x≦1,0≦y≦1, 0≦x+y≦1, arbitrary composition) can be formed. Furthermore, vapordeposition, ion plating, laser abrasion, or ECR can be employed. When abuffer layer is to be formed by physical vapor deposition, physicalvapor deposition is performed preferably at 200-600° C., more preferably300-500° C., most preferably 350-450° C. When physical vapor deposition,such as sputtering, is employed, the thickness of a buffer layer ispreferably 100-3000 angstroms, more preferably 100-500 angstroms, mostpreferably 100-300 angstroms. A Group III nitride compound semiconductorlayer and/or the upper layer of a Group III nitride compoundsemiconductor as a seed for lateral epitaxial growth can be a layer(underlying layer) comprising repetitions of unit of a buffer layer anda monocrystalline Group III nitride compound semiconductor layer may beformed. The underlying layer may most preferably comprises amonocrystalline layer as the uppermost layer, which may function as aseed of lateral epitaxial growth.

[0071] The present invention is substantially applicable even when thecomposition of a buffer layer, a Group III nitride compoundsemiconductor layer functioning as a seed of lateral epitaxial growth, alayer which epitaxially grows in lateral direction, and/or a Group IIInitride compound semiconductor which is placed at the upper surface, aresuch that a portion of Group III elements are replaced with boron (B) orthallium (Tl) or a portion of nitrogen (N) atoms are replaced withphosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). Also, thebuffer layer and the Group III nitride compound semiconductor may bedoped with any one of these elements to such an extent as not to appearin the composition thereof. For example, a Group III nitride compoundsemiconductor which is represented by Al_(x)Ga_(1−x)N (0≦x≦1) and whichdoes not contain indium (In) and arsenic (As) may be doped with indium(In), which is larger in atomic radius than aluminum (Al) and gallium(Ga), or arsenic (As), which is larger in atomic radius than nitrogen(N), to thereby improve crystallinity through compensation, by means ofcompression strain, for crystalline expansion strain induced by droppingoff of nitrogen atoms. In this case, since acceptor impurities easilyoccupy the positions of Group III atoms, p-type crystals can be obtainedas grown. Through the thus-attained improvement of crystallinitycombined with the features of the present invention, threadingdislocation can be further reduced to approximately {fraction (1/100)}to {fraction (1/1000)}. In the case where a light-emitting device is atarget product, use of a binary or ternary Group III nitride compoundsemiconductor is preferred.

[0072] When an n-type Group III nitride compound semiconductor layer isto be formed, a Group IV or Group VI element, such as Si, Ge, Se, Te, orC, can be added as an n-type impurity. A Group II or Group IV element,such as Zn, Mg, Be, Ca, Sr, or Ba, can be added as a p-type impurity.The same layer may be doped with a plurality of n-type or p-typeimpurities or doped with both n-type and p-type impurities.

[0073] Preferably, the front of lateral epitaxial growth isperpendicular to a substrate. However, lateral epitaxial growth mayprogress while slant facets with respect to the substrate aremaintained.

[0074] Preferably, lateral epitaxial growth progresses such that atleast an upper portion of the front of lateral epitaxial growth isperpendicular to the surface of a substrate. More preferably, growthfronts are {11-20} planes of a Group III nitride compound semiconductor.

[0075] The depth and width of trenches to be etched is determined suchthat lateral epitaxial growth fills the trenches. Conditions of etchingare determined while utilizing the phenomenon that vertical growth fromthe surface of a substrate or from a different layer does not take placeor is very slow in at least the initial stage of growth.

[0076] When the crystal orientation of a Group III nitride compoundsemiconductor layer to be formed on a substrate can be predicted,masking or dicing sidewalls of the trenches formed at the substrate inthe form of stripes parallel to the a-plane ({11-20} plane) or them-plane ({1-100} plane) of the Group III nitride compound semiconductorlayer is favorable. The aforementioned stripe or mask patterns may beisland-like or grid-like or may assume other forms. The front of lateralepitaxial growth may be perpendicular or oblique to the surface of asubstrate. In order for the a-plane; i.e., the {11-20} plane, of a GroupIII nitride compound semiconductor layer to become the front of lateralepitaxial growth, the longitudinal direction of stripes must, forexample, be perpendicular to the m-plane; i.e., the {1-100} plane, ofthe Group III nitride compound semiconductor layer. For example, whenthe surface of a substrate. is the a-plane or the c-plane of sapphire,the m-plane of sapphire usually matches the a-plane of a Group IIInitride compound semiconductor layer formed on the substrate. Thus,dicing is performed according to the arrangement of the planes. In thecase of a point-like, grid-like, or island-like etching, planes thatdefine an outline (sidewalls) are preferably {11-20} planes of the GroupIII nitride compound semiconductor layer which is formed as an upperlayer.

[0077] An etching mask may comprise an oxide or nitride, such as siliconoxide (SiO₂), silicon nitride (Si₃N₄), titanium oxide (TiO_(x)), orzirconium oxide (ZrO_(x)); or may assume the form of a multi-layer filmthereof. The etching mask may be formed by a vapor phase growth process,such as vapor deposition, sputtering, or CVD, or other processes.

[0078] Reactive ion beam etching (RIE) is preferred, but any otheretching process may be employed. Alternative to etching, trenches may beformed by using a mechanical process such as scribing can be used. Anyother arbitrary process, for example, scribing, using a diamond cutter,can be also used to roughen the substrate.

[0079] A semiconductor device, such as an FET or a light-emittingdevice, can be formed on the above-described Group III nitride compoundsemiconductor having regions where threading dislocation is suppressed,throughout the entire region or mainly on the regions where threadingdislocation is suppressed. In the case of a light-emitting device, alight-emitting layer assumes a multi-quantum well (MQW) structure, asingle-quantum well (SQW) structure, a homo-structure, asingle-hetero-structure, or a double-hetero-structure, or may be formedby means of, for example, a pin junction or a pn junction.

[0080] The above-described Group III nitride compound semiconductorhaving regions where threading dislocation is suppressed can be formedinto a Group III nitride compound semiconductor substrate throughremoval of, for example, the substrate 1, the buffer layer 2, andportions of the Group III nitride compound semiconductor where threadingdislocation is not suppressed. The thus-formed substrate allowsformation of a Group III nitride compound semiconductor device thereonor may be used as a substrate for forming a greater Group III nitridecompound semiconductor crystal. The removal can be performed bymechanochemical polishing or any other appropriate process.

[0081] After treating the substrate and forming regions with lessthreading dislocations, regions with less threading dislocations areformed on the upper portion of the regions with much threadingdislocations. That is also included in the present invention as analternative example. For example, according to the first to fourthfeatures of the present invention, a mask is formed on the regions withmuch threading dislocations, which are formed in the Group III nitridecompound semiconductor layer comprising regions with less threadingdislocations and regions with much threading dislocations. Thenepitaxially growing the Group III nitride compound semiconductor layerin lateral direction with the surface of the regions with less threadingdislocations, on which no mask is formed, serving as a seed for crystalgrowth, and covering the upper portion of the mask, thereby obtaining aGroup III nitride compound semiconductor layer with generally lessthreading dislocations. As an other alternative, a second lateralepitaxial growth on the upper portion of the regions with much threadingdislocations may be carried on.

[0082] The present invention will next be described with reference tospecific embodiments. The embodiments will be described while mentioninga method for fabricating a light-emitting device. However, the presentinvention is not limited to the embodiments to be described below. Thepresent invention discloses a method for fabricating a Group III nitridecompound semiconductor applicable to fabrication of any device.

[0083] In all the embodiments to be described below, the Group IIInitride compound semiconductor of the present invention was fabricatedby metal-organic vapor phase epitaxy (hereinafter called “MOVPE”).Typical gases used include ammonia (NH₃), carrier gas (H₂ or N₂),trimethylgallium (Ga(CH₃)₃, hereinafter called “TMG”), trimethylaluminum(Al(CH₃)₃, hereinafter called “TMA”), trimethylindium (In(CH₃)₃,hereinafter called “TMI”), and cyclopentadienylmagnesium (Mg(C₅H₅)₂,hereinafter called “Cp₂Mg”).

[0084] [First Embodiment]

[0085] A monocrystalline sapphire substrate 1 was prepared such that thea-plane thereof cleaned through organic cleaning and heat treatmentserves as the main surface thereof. By carrying out dicing, trencheseach having a width of 10 μm and a depth of 10 μm were formed at 10 μmof intervals in a stripe pattern. Next, temperature was set to 400° C.,and H₂ (10 L/min), NH₃ (5 L/min), and TMA (20 μmol/min) were suppliedfor approximately 3 minutes to thereby form, on the sapphire substrate1, a buffer layer 2 of AlN having a thickness of approximately 40 nm.The buffer layer 2 was formed mainly on the upper surface and the bottomsurface of the trenches of the substrate 1.

[0086] Next, while the temperature of the sapphire substrate 1 wasmaintained at 1150° C., H₂ (20 L/min), NH₃ (10 L/min), and TMG (5μmol/min) were introduced to thereby form a GaN layer 3 through verticaland lateral epitaxial growth. At this time, lateral epitaxial growthfrom the buffer layer 21, which was mainly formed on the upper surfaceof the posts, filled the trenches and thus establishing a flat topsurface (FIG. 1(c)). Subsequently, H₂ (20 L/min), NH₃ (10 L/min), andTMG (300 μmol/min) were introduced to thereby grow the GaN layer 3 suchthat the thickness of the GaN layer 3 becomes 10 μm of thickness. Incontrast to portions of the GaN layer 3 formed above the top surfaces ofthe posts, portions of the GaN layer 32 formed above the bottoms of thetrenches extending as deep as 10 μm through the substrate 1 exhibitedsignificant suppression of threading dislocation.

[0087] [Second Embodiment]

[0088] A monocrystalline sapphire substrate 1 was prepared such that thea-plane thereof cleaned through organic cleaning and heat treatmentserves as the main surface thereof. Temperature was dropped to 400° C.,and H₂ (10 L/min), NH₃ (5 L/min), and TMA (20 μmol/min) were suppliedfor approximately 3 minutes to thereby form, on the sapphire substrate1, an AlN layer (first buffer layer) 2 having a thickness ofapproximately 40 nm. Next, by carrying out dicing, trenches each havinga width of 10 μm and a depth of 10 μm were formed at 10 μm of intervalsin a stripe pattern. The buffer layer 2 remained only on the uppersurface of posts of the substrate 1 (FIG. 5(b)).

[0089] Next, while the temperature of the sapphire substrate 1 wasmaintained at 1150° C., H₂ (20 L/min), NH₃ (10 L/min), and TMG (5μmol/min) were introduced to thereby form a GaN layer 3 was formedthrough vertical and lateral epitaxial growth. At this time, lateralepitaxial growth from the buffer layer 21, which was mainly formed onthe upper surface of the posts, filled the trenches and thusestablishing a flat top surface (FIGS. 5(c) and 5(d)). Subsequently, H₂(20 L/min), NH₃ (10 L/min), and TMG (300 μmol/min) were introduced tothereby grow the GaN layer 3 such that the thickness of the GaN layer 3becomes 10 μm. In contrast to portions of the GaN layer 3 formed abovethe top surfaces of the posts, portions formed above the bottoms of thetrenches extending as deep as 10 μm through the substrate 1 exhibitedsignificant suppression of threading dislocation.

[0090] [Third Embodiment]

[0091] A monocrystalline sapphire substrate 1 was prepared such that thea-plane thereof cleaned through organic cleaning and heat treatmentserves as the main surface thereof. Then the surface of the substrate 1was selectively dry-etched in a short time by reactive ion beam etching(RIE) to have stripe-shaped ruggedness each having a width of 10 μm atintervals of 10 μm. Next, while the temperature of the sapphiresubstrate 1 was maintained at 400° C., H₂ (10 L/min), NH₃ (5 L/min), andTMA (20 μmol/min) were introduced for 3 minutes to thereby form an AlNbuffer layer 2 having a thickness of about 40 nm. The surface morphologyof the rugged portion 22 was different from that of the smooth portion21 of the buffer layer 2 (FIG. 7(b)).

[0092] Next, while the temperature of the substrate 1 was maintained at1150° C., H₂ (20 L/min), NH₃ (10 L/min), and TMA (5 μmol/min) wereintroduced to thereby form a GaN layer 3 through vertical and lateralepitaxial growth. At this time, mainly the lateral epitaxial growth fromthe smooth portion 21 covers the rugged portion 22 of the buffer layer2, thereby obtain a flat surface (FIGS. 7 (c) and 7 (d)). Then H₂ (20L/min), NH₃ (10 L/min), and TMG (300 μmol/min) were introduced tothereby form a GaN layer 3 having a thickness of 3 μm. In contrast toportions of the GaN layer 3 formed above the top surfaces of the posts,portions of the GaN layer 3 formed above the bottoms of the trenchesextending as deep as 10 μm through the substrate 1 exhibited significantsuppression of threading dislocation.

[0093] [Fourth Embodiment]

[0094] The present embodiment used an underlying layer comprisingrepetitions of a buffer layer and a monocrystalline Group III nitridecompound semiconductor layer as shown in FIG. 12. A monocrystallinesapphire substrate 1 was prepared such that the a-plane thereof cleanedthrough organic cleaning and heat treatment serves as the main surfacethereof. Temperature was dropped to 400° C., and H₂ (10 L/min), NH₃ (5L/min), and TMA (20 μmol/min) were supplied for approximately 3 minutesto thereby form, on the sapphire substrate 1, a first AlN layer 211having a thickness of approximately 40 nm. Next, while the temperatureof the sapphire substrate 1 was maintained at 1000° C., H₂ (20 L/min),NH₃ (10 L/min), and TMG (300 μmol/min) were introduced to thereby form aGaN layer 212 having a thickness of approximately 0.3 μm. Next, thetemperature was dropped to 400° C., and H₂ (10 L/min), NH₃ (5 L/min),and TMA (20 μmol/min) were supplied for approximately 3 minutes tothereby form a second AlN layer 213 having. a thickness of approximately40 nm. Thus was formed an underlying layer 20 comprising the first AlNlayer 211 having a thickness of approximately 40 nm, the GaN layer 212having a thickness of approximately 0.3 μm, and the second AlN layer 213having a thickness of approximately 40 nm.

[0095] Next, trenches are formed by dicing in a manner similar to thatof the second embodiment. The trenches were caused to extend by a depthof 10 μm into the sapphire substrate 1. Next, while the temperature ofthe sapphire substrate 1 was maintained at 1150° C., H₂ (20 L/min), NH₃(10 L/min), and TMG (5 μmol/min) were introduced to thereby form a GaNlayer 3 through lateral epitaxial growth. Lateral epitaxial growth wasperformed while the underlying layer 20 formed at the top portions ofthe posts served as seeds for crystal growth, thereby filling thetrenches and thus establishing a flat top surface. Subsequently, H₂ (20L/min), NH₃ (10 L/min), and TMG (300 μmol/min) were introduced tothereby grow the GaN layer 3 such that the GaN layer 3 has a thicknessof 10 μm. In contrast to portions of the GaN layer 3 formed above thetop surfaces of the posts, portions of the GaN layer 3 formed above the10 μm-depth portions of the trenches formed in the sapphire substrate 1exhibited significant suppression of threading dislocation.

[0096] [Fifth Embodiment]

[0097] On a wafer formed in a manner similar to that of the firstembodiment, a laser diode (LD) 100 shown in FIG. 13 was formed in thefollowing manner. Notably, in formation of the GaN layer 3, silane(SiH₄) was introduced so as to form a silicon (Si)-doped n-type GaNlayer serving as the GaN layer 3. For the sake of simplifiedillustration, the drawing merely illustrates a wafer 1000 to inclusivelyrepresent the trenched sapphire substrate 1, the buffer layer 2 which isformed on the upper surface of the posts and the bottom surface of thetrenches, and the GaN layer which fills the trenches as well asillustrates a GaN layer 103 to represent the remaining portion of theGaN layer 3.

[0098] On the n-type GaN layer 103 formed on the wafer layer 1000comprising the trenched sapphire substrate 1, the AlN buffer layer 2,and the GaN layer 3, an n-clad layer 104 of silicon (Si)-dopedAl_(0.08)Ga_(0.92)N, an n-guide layer 105 of silicon (Si)-doped GaN, anMQW-structured light-emitting layer 106, a p-guide layer 107 ofmagnesium (Mg)-doped GaN, a p-clad layer 108 of magnesium (Mg)-dopedAl_(0.08)Ga_(0.92)N, and a p-contact layer 109 of magnesium (Mg)-dopedGaN were formed. Next, an electrode 110A of gold (Au) was formed on thep-contact layer 109. Etching was partially performed until thethree-layered GaN layer 103 consisting of the two-layered GaN layer andthe n-type GaN layer was exposed. On the exposed GaN layer 103, anelectrode 110B of aluminum (Al) was formed. The thus-formed laser diode(LD) exhibited the significant improvement of device life andlight-emitting efficiency.

[0099] [Sixth Embodiment]

[0100] On a wafer formed in a manner similar to that of the firstembodiment, a light-emitting diode (LED) 200 shown in FIG. 14 was formedin the following manner. When the GaN layer 3 is formed, silane (SiH₄)was introduced so that the GaN layer 3 comprises Si-doped n-type GaN.For the sake of simplified illustration, the drawing merely illustratesa wafer 2000 to inclusively represent the trenched sapphire substrate 1,the buffer layer 2 which is formed on the upper surface of the posts andthe bottom surface of the trenches, and the GaN layer which fills thetrenches as well as illustrates a GaN layer 203 to represent theremaining portion of the GaN layer 3.

[0101] On the n-type GaN layer 203 formed on the wafer layer 2000comprising the trenched sapphire substrate 1, the AlN buffer layer 2,and the GaN layer 3 which fills the trenches, an n-clad layer 204 ofsilicon (Si)-doped Al_(0.08)Ga_(0.92)N, a light-emitting layer 205, ap-clad layer 206 of magnesium (Mg)-doped Al_(0.08)Ga_(0.92)N, and ap-contact layer 207 of magnesium (Mg)-doped GaN were formed. Next, anelectrode 208A of gold (Au) was formed on the p-contact layer 207.Etching was partially performed until the two-layered GaN layer 203consisting of the GaN layer and the n-type GaN layer was exposed. On theexposed GaN layer 203, an electrode 208B of aluminum (Al) was formed.The thus-formed light-emitting diode (LED) exhibited the significantimprovement of device life and light-emitting efficiency.

[0102] [Seventh Embodiment]

[0103] The present embodiment used a silicon (Si) substrate. The Sisubstrate 301 was etched in a stripe pattern and trenches each having awidth of 10 μm and a depth of 10 μm were formed at 10 μm of intervals ina stripe pattern. Next, while the temperature of the silicon substrate301 was maintained at 1150° C., H₂ (20 L/min), NH₃ (10 L/min), TMG (5μmol/min), TMA (0.5 μmol/min), and silane (SiH₄) diluted with H₂ gas(0.01 μmol/min) were introduced to thereby grow an n-Al_(0.15)Ga_(0.85)Nlayer vertically from the bottom surfaces of the trenches on the siliconsubstrate and laterally from the top surface of the posts and thesidewalls of the trenches in the silicon substrate. Lateral epitaxialgrowth was performed while the surfaces of upper portions of the postsprimarily served as seeds, thereby filling the trenches formed in thesubstrate and thus establishing a flat top surface. Subsequently, H₂ (10L/min), NH₃ (10 L/min), TMG (100 μmol/min), TMA (10 μmol/min), andsilane (SiH₄) diluted with H₂ gas (0.2 μmol/min) were introduced tothereby grow the n-Al_(0.15)Ga_(0.85)N layer to a thickness of 3 μm.Hereinafter, the trenched silicon substrate 301 and then-Al_(0.15)Ga_(0.85)N layer 302 are inclusively represented by a wafer3000.

[0104] On the wafer 3000 (the trenched silicon substrate 301 and then-Al_(0.15)Ga_(0.85)N layer 302 formed on the substrate 301), an n-guidelayer 303 of silicon (Si)-doped GaN, an MQW-structured light-emittinglayer 304, a p-guide layer 305 of magnesium (Mg)-doped GaN, a p-cladlayer 306 of magnesium (Mg)-doped Al_(0.08)Ga_(0.92)N, and a p-contactlayer 307 of magnesium (Mg)-doped GaN were formed. Next, an electrode308A of gold (Au) was formed on the p-contact layer 307, and anelectrode 308B of aluminum (Al) was formed on the back side of thesilicon substrate 301. The thus-formed laser diode (LD) 300 of FIG. 15exhibited the significant improvement of device life and light-emittingefficiency.

[0105] [Eighth Embodiment]

[0106] The present embodiment used a silicon (Si) substrate. As in theseventh embodiment which used a wafer comprising the trenched siliconsubstrate 301 and the n-Al_(0.15)Ga_(0.85)N layer 302 formed thereon,the present embodiment used a wafer 4000 comprising a trenchedsilicon-substrate 401 and an n-Al_(0.15)Ga_(0.85)N layer 402 formed onthe substrate 401. On the wafer 4000, a light-emitting layer 403 and ap-clad layer 404 of magnesium (Mg)-doped Al_(0.15)Ga_(0.85)N wereformed. Next, an electrode 405A of gold (Au) was formed on the p-cladlayer 404, and an electrode 405B of aluminum (Al) was formed on the backside of the silicon substrate 401. The thus-formed light-emitting diode(LED) 400 of FIG. 16 exhibited the significant improvement of devicelife and light-emitting efficiency.

[0107] [Modification of Etching]

[0108] The embodiment allow formation of island-like posts or formationof rugged portions B and smooth portions as shown, in FIG. 17. Tofacilitate understanding, the schematic view of FIG. 17(a) includes aperipheral region. In actuality, tens of millions of island-like postsmay be formed per wafer. In FIG. 17(a), the area of the bottoms of thetrenches B is 3 times the area of the top surfaces of the island-likeposts. In FIG. 17(b), the area of the bottoms of the trenches B is 8times the area of the top surfaces of the island-like posts.

[0109] While the present invention has been described with reference tothe above embodiments, the present invention is not limited thereto, butmay be modified as appropriate without departing from the spirit of theinvention.

[0110] The entire disclosures and contents of Japanese PatentApplication No. 2000-71350, from which the present invention claimsconvention priority, are incorporated herein by reference.

1. A method for fabricating a Group III nitride compound semiconductor on a substrate, comprising the steps of: removing at least a portion of the surface of said substrate, so as to provide a trench/post on the surface of said substrate; and epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the upper portion of the trench of said trench/post of said substrate, with a top surface of said substrate which is not removed serving as a seed for crystal growth, wherein the remaining surface of said substrate being formed by removing the surface of said substrate so as to form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 2. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is formed on a buffer layer formed on a substrate, comprising the steps of: removing at least a portion of the surface of said substrate, so as to provide a trench/post on the surface of said substrate; forming said buffer layer on said substrate; and epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the upper portion of the trench of said trench/post of said substrate, with said buffer layer formed on the remaining surface of said substrate serving as a seed for crystal growth, wherein said buffer layer being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 3. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is formed on a buffer layer formed on a substrate, comprising the steps of: removing at least a portion of the surface of said substrate, so as to provide a trench/post on the surface of said substrate; forming a buffer layer on said substrate; epitaxially growing, vertically, a Group III nitride compound semiconductor on said buffer layer so as to form a monocrystalline layer; and epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the upper portion of the trench of said trench/post of said substrate, with said monocrystalline layer of said Group III nitride compound semiconductor formed on said buffer layer on the remaining surface of said substrate serving as a seed for crystal growth, wherein said monocrystalline layer is formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 4. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is formed on a buffer layer formed on a substrate, comprising the steps of: forming said buffer layer on said substrate; removing at least a portion of said buffer layer and the surface of said substrate so as to provide a trench/post having a post on which said buffer layer is formed on the surface of said substrate and a trench on which said buffer layer is not formed; and epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the upper portion of the trench of said trench/post of said substrate, with said buffer layer formed on the remaining surface of said substrate serving as a seed for crystal growth, wherein said buffer layer being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 5. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is formed on a buffer layer formed on a substrate, comprising the steps of: forming said buffer layer on said substrate; epitaxially growing, vertically, a Group III nitride compound semiconductor on said buffer layer so as to form a monocrystalline layer; removing at least a portion of said monocrystalline layer of said Group III nitride compound semiconductor, said buffer layer, and the surface of said substrate so as to provide a trench/post having a post on which said monocrystalline layer of said Group III nitride compound semiconductor and said buffer layer is formed on said surface of said substrate and a trench on which said monocrystalline layer of said Group III nitride compound semiconductor and said buffer layer are not formed; and epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the upper portion of the trench of said trench/post of said substrate, with said monocrystalline layer of Group III nitride compound semiconductor formed on said buffer layer on the remaining surface of said substrate serving as a seed for crystal growth, wherein said monocrystalline layer being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 6. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is grown on a substrate, comprising the steps of: a surface treatment process of decreasing smoothness of at least a portion of the surface of said substrate and forming a portion on which a Group III nitride compound semiconductor is not sufficiently to be formed on the surface of said substrate; a process of growing said Group III nitride compound semiconductor on said treated substrate and forming a portion where a monocrystalline layer of said Group III nitride compound semiconductor is sufficiently formed and a portion where a monocrystalline layer of said Group III nitride compound semiconductor is not sufficiently formed; and a process of epitaxially growing, vertically and laterally, a Group III nitride compound semiconductor, so as to cover the portion where said monocrystalline layer of said Group III nitride compound semiconductor is not sufficiently formed, with said monocrystalline layer of said Group III nitride compound semiconductor formed on the portion of said substrate whose surface smoothness is not decreased serving as a seed for crystal growth, wherein said monocrystalline layer being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 7. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is grown on a buffer layer formed on a substrate, comprising the steps of: a surface treatment process of decreasing smoothness of at least a portion of the surface of said substrate and forming a portion on which said buffer layer is sufficiently to be formed on the surface of said substrate; a process of growing said buffer layer on said treated substrate and forming a portion where said buffer layer is sufficiently formed and a portion where said buffer layer is not sufficiently formed; and a process of epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the portion where said buffer layer is not sufficiently formed, with said buffer layer formed on the portion of said substrate whose surface smoothness is not decreased serving as a seed for crystal growth, wherein said buffer layer being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 8. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is grown on a buffer layer formed on a substrate, comprising the steps of: a surface treatment process of decreasing smoothness of at least a portion of the surface of said substrate and forming a portion on which said buffer layer is sufficiently to be formed on the surface of said substrate; a process of growing said buffer layer on said treated substrate and forming a portion where said buffer layer is sufficiently formed and a portion where said buffer layer is not sufficiently formed; a process of forming a monocrystalline layer of Group III nitride compound semiconductor on the portion where said buffer layer is sufficiently formed; and a process of epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the portion where said buffer layer is not sufficiently formed, with said monocrystalline layer of said Group III nitride compound semiconductor on said buffer layer formed on the portion of said substrate whose surface smoothness is not decreased serving as a seed for crystal growth, wherein said monocrystalline layer of said Group III nitride compound semiconductor being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 9. A method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is grown on a buffer layer formed on a substrate, comprising the steps of: a process of forming a buffer layer on a substrate; a surface treatment process of decreasing smoothness of at least a portion of the surface of said buffer layer and forming a portion on which a monocrystalline layer of a Group III nitride compound semiconductor is not sufficiently to be formed; a process of epitaxially growing, vertically and laterally, a desired Group III nitride compound semiconductor, so as to cover the portion where smoothness of said buffer layer is decreased, with the portion of said buffer layer. whose surface smoothness is not decreased serving as a seed for crystal growth, wherein the portion of said buffer layer being formed in island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 10. a method for fabricating a Group III nitride compound semiconductor in which a Group III nitride compound semiconductor is grown on a buffer layer formed on a substrate, comprising the steps of: a process of forming a buffer layer on a substrate; a process of forming a first Group III nitride compound semiconductor on said buffer layer; a surface treatment process of decreasing smoothness of at least a portion of said first Group III nitride compound semiconductor and forming a portion on which a monocrystalline layer of a second Group III nitride compound semiconductor is not sufficiently to be formed; and a process of epitaxially growing, vertically and laterally, said second Group III nitride compound semiconductor, so as to cover the portion where smoothness of said first Group III nitride compound semiconductor is decreased, with the portion of said first Group III nitride compound semiconductor whose surface smoothness is not decreased serving as a seed for crystal growth, wherein the portion of said first Group III nitride compound semiconductor being formed in an island-like structure such as a dot-like, stripe-shaped, or grid-like structure.
 11. A Group III nitride compound semiconductor device, which is formed as an upper layer provided on a lateral-epitaxially grown portion of a Group III nitride compound semiconductor layer produced through a method for fabricating a Group III nitride compound semiconductor according to any one of claims 1-10.
 12. A Group III nitride compound semiconductor light-emitting device, which is produced by stacking, as an upper layer, a different Group III nitride compound semiconductor layer on a lateral-epitaxially grown portion of a Group III nitride compound semiconductor layer produced through a method for fabricating a Group III nitride compound semiconductor according to any one of claims 1-10.
 13. A method for fabricating a Group III nitride compound semiconductor substrate including a method for fabricating a Group III nitride compound semiconductor according to any one of claims 1-10 and removing substantially entire portions except for an upper layer formed on a portion provided through lateral epitaxial growth, to thereby obtain a Group III nitride compound semiconductor substrate. 